(1) Field of the Invention
This invention relates to a data processing apparatus comprising a CPU, a memory to store instructions, a memory to store data, and peripherals including, for example, a direct memory access controller (DMAC).
(2) Description of the Related Art
With improvement of micro electronics technology, data processing apparatuses in which CPU, memories and their peripherals are packaged into one chip have been prevalent. Generally, such a data processing apparatus is constructed so that all of its processor core, internal ROM/RAM for respectively storing instructions and data, and internal peripherals are mounted on a single chip.
FIG. 1 shows the construction of the data processing apparatus as a first example of the related art. The data processing apparatus is composed of an instruction decoder 1001 for decoding instruction codes to control operations of each unit, a program counter (PC) unit 1002 for calculating instruction addresses to be executed next, a data path unit 1003 for performing arithmetic by, for example, an arithmetic and logic unit, an internal ROM 1004 for storing instructions, an internal RAM 1005 for storing data, internal peripherals 1006 including DMAC and a timer, and a bus interface unit 1007 for controlling data transfer between the units 1001-1003 which are referred to as the processor core and the units 1004-1006 which are referred to as the on-chip resources.
The bus interface unit 1007 has an instruction fetch buffer 1011, an instruction address buffer 1012, an operand address buffer 1013, a load buffer 1014, and a store buffer 1015 for temporarily storing instruction codes, instruction addresses, operand addresses, data loaded by the data path unit 1003, and data stored by the unit 1003 respectively. The bus interface unit 1007 further has an external bus interface (I/F) unit 1016 for controlling data transfer to or from external address/data buses, and a bus control unit 1017 for controlling these buffers and outputting control signals to each of the internal ROM 1004, internal RAM 1005, internal peripherals 1006, and the external address/data buses.
The data processing apparatus constructed as above is operated as follows:
To transfer instructions or data, the processor core and the on-chip resources are interconnected by a single address bus and a single data bus. This may cause contention for bus access, so that to avoid bus conflicts, the bus control unit 1017 arbitrates bus access by, for example, giving precedence to one over the other.
FIG. 2 shows the construction of the data processing apparatus as a second example of the related art. The construction is the same as that of the first example shown in FIG. 1 except for the following aspects.
To avoid bus conflicts which can be caused between fetching instructions and loading/storing data, instruction data/address buffers 1111/1112 are directly connected to the internal ROM 1004 through a pair of exclusive address/data buses, while an operand address buffer 1113, a load buffer 1114, and a store buffer 1115 together share a pair of common internal address/data buses to communicate with the internal RAM 1105, peripherals 1106 and an external bus I/F unit 1116.
This construction of the second example makes it possible to fetch an instruction and to access data at the same time. For example, an instruction can be fetched from the internal ROM 1104 to the instruction decoder 1101 while data is being accessed from the data path unit 1103 to the internal RAM 1105.
However, these data processing apparatuses have respective problems as follows:
According to the first example, too small data throughput in the buses, as compared with the data processing capacity of the processor core, prevents enhancing the performance of the data processing apparatus. For example, while the data bus is occupied for fetching an instruction code from the internal ROM 1004 to the instruction decoder 1001, the internal RAM 1005 or the peripherals 1006 cannot be accessed. In the same manner, while the data bus is occupied for loading/storing data from/to the internal RAM 1005, the internal ROM 1004 cannot fetch an instruction code.
Furthermore, the load capacity of the address/data buses is increased by a large number of hardware resources connected therewith. This causes waveform distortion, preventing clock frequency improvement.
According to the second example, on the other hand, the data path unit 1103, which cannot directly read operand data (constant data used for executing an instruction, for instance) from the internal ROM 1104, must receive such operand data from the instruction decoder 1101 by way of a ROM data transfer bus. This causes considerable deterioration to the performance of the data processing apparatus.